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Cell, AMD Chips to Power New IBM Supercomputer


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For the past three consecutive years, a computer IBM built for the US Department of Energy called BlueGene/L, powered by over 131,000 massively parallel PowerPC processors, has reigned supreme over the Top 500 Supercomputers list, now published twice annually by the University of Mannheim.

While Intel processors have dominated the rest of the list, with as many as one-third of the systems running parallel Xeons, Itaniums or Itanium 2s, Intel's dream to topple the aging PowerPC architecture may be crushed by an alliance between its two arch-rivals, IBM and AMD.

Many expected IBM at some time in the near future to be commissioned to build a new supercomputer based on its own Cell architecture, which utilizes PowerPCs in tandem with newer "synergistic processing elements" (SPEs). But buried amid yesterday's news from IBM is the revelation that "Roadrunner" -- the current designation for the computer that may run circles around BlueGene/L -- will be a hybrid, mixing over 16,000 Cells with at least as many AMD Opteron processors.

Despite that fact, IBM is predicting Roadrunner will be capable of surpassing a modern milestone: specifically, the next great metric prefix. It is aiming for a peak performance of 1.6 trillion calculations per second, or 1.6 petaflops, hurdling it above the 1 petaflop mark for the first time. Today, BlueGene/L has a theoretical peak performance of 367,000 gigaflops (billions of calculations per second), based on Top 500 estimates.

Last year, at least a few IBM engineers were boasting of the possibility of replacing PowerPCs in the basic BlueGene design with Cell processors, and perhaps boosting peak performance past that magical milestone. But are AMD processors really necessary to achieve this goal? If you had asked these same engineers last year, they would have said no.

As IBM has explained in the past, both Intel's EM64T and AMD64 architectures approach the problem of compounding processor power using a linear scale: for more power, you pack on more cores. By contrast, Cell processors use SPEs, which rely upon a PowerPC (PPE) to divide tasks into subtasks, but then work not so much in parallel but in tandem.

As a result, we've been told, to improve performance, you don't stack on more Cells on top of Cells, but instead you build clusters of SPEs, the total number of which, for efficiency's sake, should be a multiple of 2. Each cluster is managed by a PPE. Theoretically, performance is improved exponentially rather than linearly.

Yesterday, IBM cited the value "over 16,000;" and 16,384 would certainly be an appropriate multiple of 2, specifically to the 14th power. But with Opteron processors scaling linearly, using the same number on the AMD side presents a bit of a mystery: What is IBM trying to accomplish, and who is it really accomplishing this for?

IBM's statement yesterday did offer a few clues. So-called "typical computing processes," the company said, will be handled by the Opteron CPU bank, including file I/O and communication. Some at AMD might say just one Opteron processor handles that job well enough, let alone 2 to the 14th power Opterons.

Meanwhile, tasks that typically consume the majority of computing resources will be delegated to the Cell bank. What exactly does the delegating in this case was left a mystery. Is it a Cell PPE that treats Opterons the same as it does SPEs? At this point, even Intel might be interested in the answers.

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