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The PCI-SIG has announced the completion of the PCIe 5.0 specification. In the history of PCI development, this may be the first time a new standard has been finished before the previous iteration had even launched in the consumer market.


“New data-intensive applications are driving demand for unprecedented levels of performance,” said Al Yanes, PCI-SIG Chairman and President. “Completing the PCIe 5.0 specification in 18 months is a major achievement, and it is due to the commitment of our members who worked diligently to evolve PCIe technology to meet the performance needs of the industry. The PCIe architecture will continue to stand as the defacto standard for high performance I/O for the foreseeable future.”




The rapid launch of PCIe 5.0 is the result of PCIe 4.0’s massive delay. PCIe 1.0 became available in 2003, followed by PCIe 2.0 in 2007 and PCIe 3.0 in 2010. (These are the dates when the standards were completed, not when motherboard hardware became available). PCIe 4.0, in contrast, wasn’t actually completed until 2017. The long delay in 4.0’s launch means that 5.0 will likely be deployed relatively quickly. As always, PCIe 5.0 will remain backward compatible with previous PCIe versions.


It’s not clear how the market will react to the quick appearance of PCIe 5.0 versus 4.0. AMD, for example, clearly intends to adopt PCIe 4.0 for its third-generation Ryzen platform, but could theoretically be planning a relatively quick migration to PCIe 5.0. Intel could theoretically planning for a fast shift to PCIe 5.0 — or the two standards might co-exist in market, with PCIe 4.0 used for less-demanding applications, while maximum performance markets push for PCIe 5.0. We haven’t seen PCIe 5.0 used as a differentiator this way before in client PCs, however, and for good reason — up until now, it’s never particularly mattered. While multi-GPU configuration performance can be impacted by PCIe lane availability, single-GPU performance has never scaled well against PCIe lanes, and I don’t recall any instance of a new GPU scaling better on a new version of PCIe at launch as compared to the immediately previous standard.




The popularity of PCIe-based SSDs and the M.2 form factor, however, have changed things. While the gap between using an SSD and an HDD is still far larger than the improvements gained when moving from a standard SATA SSD to an M.2 drive, opening up the throttle on PCIe 5.0 will really give NAND and Optane room to stretch their collective legs. A PCIe 3.0 M.2 drive with an x4 connection provides up to 4GB/s of bandwidth in each direction. PCIe 4.0 doubles this to 8GB. PCIe 5.0 doubles it again, to 16GB.


Not only does this mean that even an x1 PCIe 5.0 link is now a heck of a lot more capable than it once was, it also means x4 drives are approaching theoretical transfer rates we used to associate with main memory not so long ago. This doesn’t actually mean NAND performs like RAM, of course. Neither Optane nor NAND are a replacement for DRAM in current client machines, and the latencies and sustained performance characteristics are entirely different. But the relatively quick jump from PCIe 3.0 to PCIe 5.0 means maximum storage performance could get substantially faster than it is already in a relatively short period of time.


The earliest we’d expect to see PCIe 5.0 adoption would be in 2020, and 2021 wouldn’t be crazy depending on how quickly Intel and AMD adopt the standard.


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Those worried that they might not have the latest should not be so. Single graphics cards hardly would be able to use up the bandwidth in 3.0 version, let alone the need for 4.0 version.


Another thing is, they are always backwards compatible there.

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PCI Express 4.0 motherboards, Solid State Drives. and other devices are not widely available yet, but that has not stopped the Peripheral Component Interconnect Special Interest Group (PCI-SIG) from releasing PCI Express 5.0 specifications on May 29, 2019.


Compared to PCI Express 4.0, PCI Express 5.0 promises double the bandwidth and other improvements while maintaining backwards compatibility with existing PCI Express peripherals.


PCI Express 4.0 doubled the bandwidth, frequency, and transfer rate of PCIe 3.0, and PCI Express 5.0 is designed to quadruple it.


Target markets for PCI Express 5.0 include gaming, visual computing, AI, storage, and machine learning.

The new specification increases performance in the high-performance markets including artificial intelligence, machine learning, gaming, visual computing, storage and networking.

Tools like HwInfo or CPU-Z may help you find out which PCI Express standards the PC you run this on supports (if any).



PCI Express 5.0 specification details

  • Bandwidth of 128 GB/s, 32 GT/s, 32.0 GHz frequency, and 128b/130b encoding.
  • Backwards compatible with all major PCI Express standards (4.0, 3.x, 2.x, and 1.x).
  • Features new backwards compatible CEM connector for add-in cards.
  • Support for extended tags and credits.
  • Electrical changes improve signal integrity and mechanical performance of connectors.

Closing Words

Most existing devices don't support PCI Express 4.0 and general availability of PCI Express 4.0 supporting hardware such as motherboards or Solid State Drives is just about to get better in 2019.


AMD announced in January 2019 that the company's X570 motherboard chipset would support PCI Express 4.0, and that some 300 and 400-series motherboards could be updated to support PCI Express 4.0 at least partially.


Phison revealed a PCIe 4.0 x4 SSD controller in January 2019 as well and managed to gain 4 GB/s of sequential reads and 4.2 of write performance out of a hardware setup back then.


With PCI Express 5.0 announced, many might wonder whether it makes senses to jump on the PCI Express 4.0 bandwagon or wait until devices that support PCI Express 5.0 come out.


PCI Express 4.0 was announced in 2017 and adoption is just about starting in the consumer market. It is not too far fetched to assume that PCI Express 5.0 will need 18 to 24 months at the minimum before devices start to become available for consumers.



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