TSMC details its 5nm and 3nm process nodes, with up to 30% more power efficiency

[Karlston]

TSMC details its 5nm and 3nm process nodes, with up to 30% more power efficiency

 

Taiwan Semiconductor, or TSMC, kicked off its 26th Technology Symposium event today, starting with a look forward at the company's upcoming processor technologies. The company discussed its 5nm nodes - N5 and N5P, the 4nm N4 node, and the 3nm N3 node, which will be coming to market over the next couple of years.

 

The N5 node is already in mass production, and it makes use of EUV technology. It promises up to a 30% improvement in power consumption or up to 15% more performance over the current N7 node, along with a 1.8x improvement in logic density. This process node is now in high volume production, so it wouldn't be surprising to see products based on it in the near future.

 

TSMC also has an enhanced 5nm node, N5P, in development, with plans to ramp up production in 2021. This will deliver a smaller 10% improvement in power consumption or a 5% in performance over the N5 node. This node is more so designed for high-performance applications.

 

The big successor to N5 is N3, TSMC's 3nm node, which will enter risk production in late 2021 and is set to enter high volume production is 2022. Once again, this transition promises between 25% and 30% improvements in power efficiency over N5, and between 10% and 15% better performance. TSMC is also planning a 4nm node, N4, for risk production in late 2021 and mass production in 2022, but not much was said about its performance improvements. It's supposed to make migration easier from the N5 node, though.

 

TSMC isn't the only foundry looking to bring 3nm nodes to market, and Samsung has said it's planning to bring its own 3nm nodes to market in 2021. The Korean company is using a different technology called Gate-All-Around, though, while TSMC is sticking with FinFET for its 3nm node.

 

TSMC is also apparently looking at the possibility of moving beyond silicon as it tries to go further than the 3nm node. While it didn't indicate any specific plans, the company mentioned technologies such as nanosheets and nanowires, and it says it has a few materials other than silicon that could let it get channel thickness below 1nm. Of course, those plans are still far in the future for now.

 

Source: Tom's Hardware

 

 

TSMC details its 5nm and 3nm process nodes, with up to 30% more power efficiency